/*
 * vme.h
 *
 *  Created on: 2012. 5. 7.
 *      Author: root
 */

#ifndef VME_H_
#define VME_H_

#define IsM_S_MODE()			(CONFIG.iCVType==0)?"MASTER":"SLAVE"
#define IsTime_MODE()			(VME.Data.TimeSync_Mode==VME_CV_MODE)?"CV_MODE":	\
											((VME.Data.TimeSync_Mode==VME_PTP_MODE)?"VME_PTP_MODE":"VME_ExtClock_MODE")
#define IsCV_Slave()			((VME.Data.TimeSync_Mode==VME_CV_MODE) && (CONFIG.iCVType==1))

#define VME_CV_MODE				0
#define VME_PTP_MODE			1
#define VME_ExtClock_MODE		2

#define VME_START_ADDR				0x200000

#define CV_TICK_SIZE				2
#define CV_DATA_MAX_SIZE			14*2*1024		//32Kbyte

#define VME_CV_START_ADDR__			(0x400)
#define VME_CV_STOP_ADDR__			(0x8000)

#define VME_ADDR_INIT				(0x00)
#define VME_ADDR_BOARDID			(0x04)
#define VME_ADDR_BIT				(0x08)
#define VME_ADDR_YEAR				(0x10)
#define VME_ADDR_MONTH_DAY			(0x14)
#define VME_ADDR_HOUR_MIN			(0x20)
#define VME_ADDR_SECOND				(0x24)
#define VME_ADDR_LAT_Deg_Min		(0x30)
#define VME_ADDR_LAT_Sec_int		(0x34)
#define VME_ADDR_LAT_Sec_Frac		(0x38)
#define VME_ADDR_LON_Deg_Min		(0x40)
#define VME_ADDR_LON_Sec_int		(0x44)
#define VME_ADDR_LON_Sec_Frac		(0x48)
#define VME_ADDR_HEIGHT				(0x50)
#define VME_ADDR_HEADING			(0x60)
#define VME_ADDR_CV					(0x70)
#define VME_ADDR_PTP_Sec			(0x80)
#define VME_ADDR_PTP_nSec_1			(0x84)
#define VME_ADDR_PTP_nSec_2			(0x88)
#define VME_ADDR_Accuracy_Sec		(0x90)
#define VME_ADDR_Accuracy_nSec_1	(0x94)
#define VME_ADDR_Accuracy_nSec_2	(0x98)
#define VME_ADDR_SYNC_MODE			(0xA0)

#define BLOCKRAM_CV_START_ADDR__		(VME_CV_START_ADDR__>>1)
#define BLOCKRAM_CV_STOP_ADDR__			(VME_CV_STOP_ADDR__>>1)

#define BLOCKRAM_ADDR_INIT				(VME_ADDR_INIT>>1)
#define BLOCKRAM_ADDR_BOARDID			(VME_ADDR_BOARDID>>1)
#define BLOCKRAM_ADDR_BIT				(VME_ADDR_BIT>>1)
#define BLOCKRAM_ADDR_YEAR				(VME_ADDR_YEAR>>1)
#define BLOCKRAM_ADDR_MONTH_DAY			(VME_ADDR_MONTH_DAY>>1)
#define BLOCKRAM_ADDR_HOUR_MIN			(VME_ADDR_HOUR_MIN>>1)
#define BLOCKRAM_ADDR_SECOND			(VME_ADDR_SECOND>>1)
#define BLOCKRAM_ADDR_LAT_Deg_Min		(VME_ADDR_LAT_Deg_Min>>1)
#define BLOCKRAM_ADDR_LAT_Sec_int		(VME_ADDR_LAT_Sec_int>>1)
#define BLOCKRAM_ADDR_LAT_Sec_Frac		(VME_ADDR_LAT_Sec_Frac>>1)
#define BLOCKRAM_ADDR_LON_Deg_Min		(VME_ADDR_LON_Deg_Min>>1)
#define BLOCKRAM_ADDR_LON_Sec_int		(VME_ADDR_LON_Sec_int>>1)
#define BLOCKRAM_ADDR_LON_Sec_Frac		(VME_ADDR_LON_Sec_Frac>>1)
#define BLOCKRAM_ADDR_HEIGHT			(VME_ADDR_HEIGHT>>1)
#define BLOCKRAM_ADDR_HEADING			(VME_ADDR_HEADING>>1)
#define BLOCKRAM_ADDR_CV				(VME_ADDR_CV>>1)
#define BLOCKRAM_ADDR_PTP_Sec			(VME_ADDR_PTP_Sec>>1)
#define BLOCKRAM_ADDR_PTP_nSec_1		(VME_ADDR_PTP_nSec_1>>1)
#define BLOCKRAM_ADDR_PTP_nSec_2		(VME_ADDR_PTP_nSec_2>>1)
#define BLOCKRAM_ADDR_Accuracy_Sec		(VME_ADDR_Accuracy_Sec>>1)
#define BLOCKRAM_ADDR_Accuracy_nSec_1	(VME_ADDR_Accuracy_nSec_1>>1)
#define BLOCKRAM_ADDR_Accuracy_nSec_2	(VME_ADDR_Accuracy_nSec_2>>1)
#define BLOCKRAM_ADDR_SYNC_MODE			(VME_ADDR_SYNC_MODE>>1)
//======================================================//
//				VME MASTER SIGNAL						//
//======================================================//
//========VME Address 15:0========//
#define VME_ADDR_0__		55//0~7bit
#define VME_ADDR_1__		56//8~15bit
#define VME_ADDR_2__		57//16~23bit

#define VME_ADDR_0(addr)	SetFpgaValue(VME_ADDR_0__, ((addr&0x1FE)>>1) )
#define VME_ADDR_1(addr)	SetFpgaValue(VME_ADDR_1__, ((addr&0x1FE00)>>9) )
#define VME_ADDR_2(addr)	SetFpgaValue(VME_ADDR_2__, ((addr&0xFE0000)>>17) )

#define VME_ADDR(addr)		do{	VME_ADDR_0(addr);	 VME_ADDR_1(addr);	 VME_ADDR_2(addr);	}while(0);


//========VME Data========//
#define VME_DATA_0__			39//0~7bit
#define VME_DATA_1__			40//7~15bit
#define VME_SIGNAL_ADDR_2		44

#define VME_DATA_EN__			wbD2
#define VME_DATA_EN_High()		SetBitHigh(VME_SIGNAL_ADDR_2,VME_DATA_EN__)
#define VME_DATA_EN_Low()		SetBitLow(VME_SIGNAL_ADDR_2,VME_DATA_EN__)

#define VME_DATA_0(v)			SetFpgaValue(VME_DATA_0__,v&0x000000FF)
#define VME_DATA_1(v)			SetFpgaValue(VME_DATA_1__,((v&0x0000FF00)>>8))


//DTACK Signal//
#define VME_DTACK_ADDR			47
#define VME_DTACK_BIT			wbD3
#define VME_ISDTACK()			IsBitHigh(VME_DTACK_ADDR,VME_DTACK_BIT)


//========VME MASTER Address========//
#define VME_DATA(data)			do{	VME_DATA_0(data);	VME_DATA_1(data);	}while(0);
#define VME_AM_ADDR 			45
#define VME_SIGNAL_ADDR_0 		42
#define VME_SIGNAL_ADDR_1 		43
//#define VME_SIGNAL_ADDR_2 		44
//========VME MASTER(1-1)========//
#define VME_AM0					wbD0
#define VME_AM1					wbD1
#define VME_AM2					wbD2
#define VME_AM3					wbD3
#define VME_AM4					wbD4
#define VME_AM5					wbD5
#define VME_CLK					wbD6
#define VME_SYSRST				wbD3
//========VME MASTER(1-2)========//
#define VME_AS					wbD0
#define VME_DS0					wbD1
#define VME_DS1					wbD2
#define VME_LWORD				wbD3
#define VME_IACK				wbD4
#define VME_IACKIN				wbD5
#define VME_WR					wbD6
#define VME_IRQ6_REQ			wbD7
//========VME MASTER(1-3)========//
#define VME_IRQ7_REQ			wbD0
#define VME_BIT_MODE_ON			wbD1
//========VME MASTER(2-1)========//
#define VME_AM0_High()			SetBitHigh(VME_AM_ADDR, VME_AM0)
#define VME_AM0_Low()			SetBitLow(VME_AM_ADDR, VME_AM0)
#define VME_AM1_High()			SetBitHigh(VME_AM_ADDR, VME_AM1)
#define VME_AM1_Low()			SetBitLow(VME_AM_ADDR, VME_AM1)
#define VME_AM2_High()			SetBitHigh(VME_AM_ADDR, VME_AM2)
#define VME_AM2_Low()			SetBitLow(VME_AM_ADDR, VME_AM2)
#define VME_AM3_High()			SetBitHigh(VME_AM_ADDR, VME_AM3)
#define VME_AM3_Low()			SetBitLow(VME_AM_ADDR, VME_AM3)
#define VME_AM4_High()			SetBitHigh(VME_AM_ADDR, VME_AM4)
#define VME_AM4_Low()			SetBitLow(VME_AM_ADDR, VME_AM4)
#define VME_AM5_High()			SetBitHigh(VME_AM_ADDR, VME_AM5)
#define VME_AM5_Low()			SetBitLow(VME_AM_ADDR, VME_AM5)
#define VME_CLK_High()			SetBitHigh(VME_SIGNAL_ADDR_0, VME_CLK)
#define VME_CLK_Low()			SetBitLow(VME_SIGNAL_ADDR_0, VME_CLK)
#define VME_SYSRST_High()		SetBitHigh(VME_SIGNAL_ADDR_2, VME_SYSRST)
#define VME_SYSRST_Low()		SetBitLow(VME_SIGNAL_ADDR_2, VME_SYSRST)
//========VME MASTER(2-2)========//
#define VME_AS_High()			SetBitHigh(VME_SIGNAL_ADDR_1, VME_AS)
#define VME_AS_Low()			SetBitLow(VME_SIGNAL_ADDR_1, VME_AS)
#define VME_DS0_High()			SetBitHigh(VME_SIGNAL_ADDR_1, VME_DS0)
#define VME_DS0_Low()			SetBitLow(VME_SIGNAL_ADDR_1, VME_DS0)
#define VME_DS1_High()			SetBitHigh(VME_SIGNAL_ADDR_1, VME_DS1)
#define VME_DS1_Low()			SetBitLow(VME_SIGNAL_ADDR_1, VME_DS1)
#define VME_LWORD_High()		SetBitHigh(VME_SIGNAL_ADDR_1, VME_LWORD)
#define VME_LWORD_Low()			SetBitLow(VME_SIGNAL_ADDR_1, VME_LWORD)
#define VME_IACK_High()			SetBitHigh(VME_SIGNAL_ADDR_1, VME_IACK)
#define VME_IACK_Low()			SetBitLow(VME_SIGNAL_ADDR_1, VME_IACK)
#define VME_IACKIN_High()		SetBitHigh(VME_SIGNAL_ADDR_1, VME_IACKIN)
#define VME_IACKIN_Low()		SetBitLow(VME_SIGNAL_ADDR_1, VME_IACKIN)
#define VME_WR_High()			SetBitHigh(VME_SIGNAL_ADDR_1, VME_WR)
#define VME_WR_Low()			SetBitLow(VME_SIGNAL_ADDR_1, VME_WR)
#define VME_IRQ6_REQ_High()		SetBitHigh(VME_SIGNAL_ADDR_1, VME_IRQ6_REQ)
#define VME_IRQ6_REQ_Low()		SetBitLow(VME_SIGNAL_ADDR_1, VME_IRQ6_REQ)
//========VME MASTER(2-3)========//
#define VME_IRQ7_REQ_High()		SetBitHigh(VME_SIGNAL_ADDR_2, VME_IRQ7_REQ)
#define VME_IRQ7_REQ_Low()		SetBitLow(VME_SIGNAL_ADDR_2, VME_IRQ7_REQ)
#define VME_BIT_MODE_ON_High()	SetBitHigh(VME_SIGNAL_ADDR_2, VME_BIT_MODE_ON)
#define VME_BIT_MODE_ON_Low()	SetBitLow(VME_SIGNAL_ADDR_2, VME_BIT_MODE_ON)

#define VME_AM()				do{ VME_AM5_High();VME_AM4_High();VME_AM3_High();VME_AM2_High();VME_AM1_Low();VME_AM0_High(); }while(0);
#define VME_AM_Clear()			do{ VME_AM5_Low();VME_AM4_Low();VME_AM3_Low();VME_AM2_Low();VME_AM1_Low();VME_AM0_Low(); }while(0);

//=========VME Master BlockRam Read========//
#define VME_M_ReadAddr_EN		44
#define VME_M_Read_EN__			wbD4

#define VME_M_Read_EN_High()	SetBitHigh(VME_M_ReadAddr_EN,VME_M_Read_EN__)
#define VME_M_Read_EN_Low()		SetBitLow(VME_M_ReadAddr_EN,VME_M_Read_EN__)

#define VME_M_BlockRam_ReadData_0	41
#define VME_M_BlockRam_ReadData_1	42

#define VME_M_ReadData_0()		GetFpgaValue(VME_M_BlockRam_ReadData_0)
#define VME_M_ReadData_1()		( (GetFpgaValue(VME_M_BlockRam_ReadData_1))<<8 )

#define VME_M_ReadData()		(	VME_M_ReadData_0() + VME_M_ReadData_1()	)





//========================================================//
//							VME SLAVE Block Ram				//
//========================================================//

#define VME_BlockRam_ADDR_0__			36
#define VME_BlockRam_ADDR_1__			37
#define VME_BlockRam_DATA_0__			38
#define VME_BlockRam_DATA_1__			39
#define VME_BlockRam_Control_Addr		42
#define VME_BlockRam_ReadData_0			40
#define VME_BlockRam_ReadData_1			41

#define VME_IOBUF_EN			wbD2
#define VME_BlockRam_wea		wbD0
//#define VME_BlockRam_regce wbD4

#define VME_BlockRam_ADDR_0(addr)	SetFpgaValue(VME_BlockRam_ADDR_0__,(addr&0xFF))
#define VME_BlockRam_ADDR_1(addr)	SetFpgaValue(VME_BlockRam_ADDR_1__,(addr&0x3F00)>>8)
#define VME_BlockRam_DATA_0(data)	SetFpgaValue(VME_BlockRam_DATA_0__,(data&0xFF))
#define VME_BlockRam_DATA_1(data)	SetFpgaValue(VME_BlockRam_DATA_1__,(data&0xFF00)>>8)

#define VME_BlockRam_ADDR(addr)		do{	VME_BlockRam_ADDR_0(addr);	VME_BlockRam_ADDR_1(addr);	}while(0);
#define VME_BlockRam_DATA(data)		do{	VME_BlockRam_DATA_0(data);	VME_BlockRam_DATA_1(data);	}while(0);

#define VME_IOBUF_EN_High()			SetBitHigh(VME_BlockRam_Control_Addr, VME_IOBUF_EN)
#define VME_IOBUF_EN_Low()			SetBitLow(VME_BlockRam_Control_Addr, VME_IOBUF_EN)
#define VME_BlockRam_wea_High()		SetBitHigh(VME_BlockRam_Control_Addr, VME_BlockRam_wea)
#define VME_BlockRam_wea_Low()		SetBitLow(VME_BlockRam_Control_Addr, VME_BlockRam_wea)
//#define VME_BlockRam_regce_High()	SetBitHigh(VME_BlockRam_Control_Addr, VME_BlockRam_regce)
//#define VME_BlockRam_regce_Low()	SetBitLow(VME_BlockRam_Control_Addr, VME_BlockRam_regce)

#define VME_ReadData_0()			GetFpgaValue(VME_BlockRam_ReadData_0)
#define VME_ReadData_1()			( (GetFpgaValue(VME_BlockRam_ReadData_1))<<8 )

#define VME_ReadData()				(	VME_ReadData_0() + VME_ReadData_1()	)



//12-05-10 sewon	Debug Output Mux
#define DATA_DIR()	 	do{SetBitLow(42,wbD4);SetBitLow(42,wbD3);}while(0)
#define DTACK()			do{SetBitLow(42,wbD4);SetBitHigh(42,wbD3);}while(0)
#define WRITE_EN()		do{SetBitHigh(42,wbD4);SetBitLow(42,wbD3);}while(0)
#define READ_EN()		do{SetBitHigh(42,wbD3);SetBitHigh(42,wbD4);}while(0)



//========================================================//
//					VME SLAVE Block Ram_B TEST			 //
//========================================================//
#define VME_BlockRam_ADDR2_0__			45
#define VME_BlockRam_ADDR2_1__			46
#define VME_BlockRam_DATA2_0__			47
#define VME_BlockRam_DATA2_1__			48
#define VME_BlockRam_Control2_Addr		42
#define VME_BlockRam_ReadData2_0		43
#define VME_BlockRam_ReadData2_1		44

#define VME_IOBUF_EN2			wbD7
#define VME_BlockRam_wea2		wbD6
//#define VME_BlockRam_regce wbD4

#define VME_BlockRam_ADDR2_0(addr)	SetFpgaValue(VME_BlockRam_ADDR2_0__,(addr&0xFF))
#define VME_BlockRam_ADDR2_1(addr)	SetFpgaValue(VME_BlockRam_ADDR2_1__,(addr&0x3F00)>>8)
#define VME_BlockRam_DATA2_0(data)	SetFpgaValue(VME_BlockRam_DATA2_0__,(data&0xFF))
#define VME_BlockRam_DATA2_1(data)	SetFpgaValue(VME_BlockRam_DATA2_1__,(data&0xFF00)>>8)

#define VME_BlockRam_ADDR2(addr)	do{	VME_BlockRam_ADDR2_0(addr);	VME_BlockRam_ADDR2_1(addr);	}while(0);
#define VME_BlockRam_DATA2(data)	do{	VME_BlockRam_DATA2_0(data);	VME_BlockRam_DATA2_1(data);	}while(0);

#define VME_IOBUF_EN2_High()		SetBitHigh(VME_BlockRam_Control2_Addr, VME_IOBUF_EN2)
#define VME_IOBUF_EN2_Low()			SetBitLow(VME_BlockRam_Control2_Addr, VME_IOBUF_EN2)
#define VME_BlockRam_wea2_High()	SetBitHigh(46, VME_BlockRam_wea2)
#define VME_BlockRam_wea2_Low()		SetBitLow(46, VME_BlockRam_wea2)
//#define VME_BlockRam_regce_High()	SetBitHigh(VME_BlockRam_Control2_Addr, VME_BlockRam_regce)
//#define VME_BlockRam_regce_Low()	SetBitLow(VME_BlockRam_Control2_Addr, VME_BlockRam_regce)

#define VME_ReadData2_0()			GetFpgaValue(VME_BlockRam_ReadData2_0)
#define VME_ReadData2_1()			( (GetFpgaValue(VME_BlockRam_ReadData2_1))<<8 )

#define VME_ReadData2()				(	VME_ReadData2_0() + VME_ReadData2_1()	)




//Slave Mux
#define SLAVE_MUX_ADDR	42

#define MUX_S0	wbD5
#define MUX_S1	wbD6
#define MUX_S2	wbD7

#define VME_MUX_AS()			do{SetBitLow(SLAVE_MUX_ADDR,MUX_S2);SetBitLow(SLAVE_MUX_ADDR,MUX_S1);SetBitLow(SLAVE_MUX_ADDR,MUX_S0);}while(0);
#define VME_MUX_DS1()			do{SetBitLow(SLAVE_MUX_ADDR,MUX_S2);SetBitLow(SLAVE_MUX_ADDR,MUX_S1);SetBitHigh(SLAVE_MUX_ADDR,MUX_S0);}while(0);
#define VME_MUX_CLK()			do{SetBitLow(SLAVE_MUX_ADDR,MUX_S2);SetBitHigh(SLAVE_MUX_ADDR,MUX_S1);SetBitLow(SLAVE_MUX_ADDR,MUX_S0);}while(0);
#define VME_MUX_LWORD()			do{SetBitLow(SLAVE_MUX_ADDR,MUX_S2);SetBitHigh(SLAVE_MUX_ADDR,MUX_S1);SetBitHigh(SLAVE_MUX_ADDR,MUX_S0);}while(0);
#define VME_MUX_IACK()			do{SetBitHigh(SLAVE_MUX_ADDR,MUX_S2);SetBitLow(SLAVE_MUX_ADDR,MUX_S1);SetBitLow(SLAVE_MUX_ADDR,MUX_S0);}while(0);
#define VME_MUX_WR()			do{SetBitHigh(SLAVE_MUX_ADDR,MUX_S2);SetBitLow(SLAVE_MUX_ADDR,MUX_S1);SetBitHigh(SLAVE_MUX_ADDR,MUX_S0);}while(0);
#define VME_MUX_IRQ6_REQ()		do{SetBitHigh(SLAVE_MUX_ADDR,MUX_S2);SetBitHigh(SLAVE_MUX_ADDR,MUX_S1);SetBitLow(SLAVE_MUX_ADDR,MUX_S0);}while(0);
#define VME_MUX_BIT_MODE()		do{SetBitHigh(SLAVE_MUX_ADDR,MUX_S2);SetBitHigh(SLAVE_MUX_ADDR,MUX_S1);SetBitHigh(SLAVE_MUX_ADDR,MUX_S0);}while(0);

//========================================================//
//					IRQ4 Interrupt Send					  //
//========================================================//
#define VME_INT_ADDR_0			55
#define VME_INT_ADDR_1			23
#define VME_INT_DATA_0			56
#define VME_INT_DATA_1			57
#define VME_CONTROL_ADDR_1		58
#define VME_CONTROL_ADDR_2		59

#define VME_IRQ4_IACK		wbD0
#define VME_IRQ4_REQ		wbD0
#define VME_WRITE_ACK		wbD4
#define VME_WRITE_REQ		wbD4

#define VME_IRQ4_IACK_IsBitHigh()	IsBitHigh(VME_CONTROL_ADDR_1,VME_IRQ4_IACK)
#define VME_IRQ4_REQ_High()			SetBitHigh(VME_CONTROL_ADDR_2,VME_IRQ4_REQ)
#define VME_IRQ4_REQ_Low()			SetBitLow(VME_CONTROL_ADDR_2,VME_IRQ4_REQ)
#define VME_WRITE_ACK_IsBitHigh()	IsBitHigh(VME_CONTROL_ADDR_1,VME_WRITE_ACK)
#define VME_WRITE_REQ_High()		SetBitHigh(VME_CONTROL_ADDR_2,VME_WRITE_REQ)
#define VME_WRITE_REQ_Low()			SetBitLow(VME_CONTROL_ADDR_2,VME_WRITE_REQ)

//========================================================//
//					VME Ext1PPS TimeSync Mode			 //
//========================================================//
#define Ext1PPS_ADDR		10

#define Ext1PPS_EN_			wbD5

#define Ext1PPS_EN_High()	SetBitHigh(Ext1PPS_ADDR,Ext1PPS_EN_)
#define Ext1PPS_EN_Low()	SetBitLow(Ext1PPS_ADDR,Ext1PPS_EN_)



void Init_VME();
void VME_Function();
void VME_Update_Data();
void VME_Update_BlockRam_Data();
void VME_Write_BlockRam();
void VME_Read_BlockRam();

void VME_Write(int addr,int data);
int VME_Read(int addr);
void VME_Interrupt();

void VME_BlockRam_Write(int addr,int data);
int VME_BlockRam_Read(int addr);

void PushCVData(char* p, unsigned int length);
void PopCVData();
int VME_CV_write(char * p, unsigned int length);

int CV_Data_Parse_string(char *cmdline, char *delim, char **argv);
int VME_CV_read();
void VME_Interrupt_handling();

typedef struct {		/* VME BlockRam Data */
	int Boart_ID;
	int Bit;
	int Year;
	int Month_Day;
	int Hour_min;
	int Second;
	int Lat_Deg_Min;
	int Lat_Sec_Int;
	int Lat_Sec_Frac;
	int Lon_Deg_min;
	int Lon_Sec_Int;
	int Lon_Sec_Frac;
	int height;
	int Heading;
	int CV;
	int PTP_Data_Sec;
	int PTP_Data_nSec_1;
	int PTP_Data_nSec_2;
	int Accuracy_Sec;
	int Accuracy_nSec_1;
	int Accuracy_nSec_2;
	int VME_Sync_Mode;

}_VME_BlockRam;

typedef struct {		/* VME Data */

	//initialize//
	int Init_Request;	//					Addr:0x200000
	int Init_Result;	//4bit	D3:D0		Addr:0x200004

	//Bit Request//
	int Bit_Request;
	unsigned char Visible;		//4bit	D15:12		Addr:0x200008
	unsigned char Tracking;		//4bit	D11:8
	unsigned char TOD_Valid;	//1bit	D4			valid(1),invalid(0)
	unsigned char FPGA_Valid;	//1bit	D3			valid(1),invalid(0)
	unsigned char Temp_Valid;	//1bit	D2			valid(1),invalid(0)
	unsigned char Power_Valid;	//1bit	D1			valid(1),invalid(0)
	unsigned char GPS_Lock;		//1bit	D0			lock(1),unlock(0)

	//TOD//
	unsigned short Year;		//12bit	D11:D0	0~4095year		Addr:0x200010
	unsigned char Month;		//4bit	D11:D8	1~12Month		Addr:0x200014
	unsigned char Day;			//5bit	D4:D0		1~31Day
	unsigned char Hour;			//5bit	D12:D8	0~23Hour			Addr:0x200020
	unsigned char Minute;		//6bit	D5:D0		0~59Minute
	unsigned char Second;		//6bit	D5:D0		0~59Second		Addr:0x200024

	//Position//
	unsigned int Lat_Degree;				//7bit	D14:8		0~90									Addr:0x200030
	unsigned char Lat_sign;					//1bit	D6			North:(0),South:(1)
	unsigned int Lat_Minute;				//6bit	D5:D0		0~59
	unsigned int Lat_Second_int;			//6bit	D5:D0		0~59									Addr:0x200034
	unsigned int Lat_Second_frac;			//14bit	D13:D0	0~9999,Resolution:0.0001sec	Addr:0x200038

	unsigned int Lon_Degree;				//7bit	D14:8		0~90									Addr:0x200040
	unsigned char Lon_sign;		//1bit	D6			North:(0),South:(1)
	unsigned int Lon_Minute;				//6bit	D5:D0		0~59
	unsigned int Lon_Second_int;			//6bit	D5:D0		0~59									Addr:0x200044
	unsigned int Lon_Second_frac;			//14bit	D13:D0	0~9999,Resolution:0.0001sec	Addr:0x200048

	unsigned char height_sign;	//1bit	D15		+:(0),-:(1),						Addr:0x200050
	unsigned int height;		//15bit	D14:D0	0~32767m,Resolusion:0.1m

	float Heading;			//16bit	D15:D0	0~359.99degree, 0~35999,Resolution:0.01	Addr:0x200060

	//CV DATA	Addr:0x200070
	//PTP DATA	Addr:0x200080

	int PTP_Data;	//ns

	unsigned int Accuracy_Sec;		//6bit	D5:D0		0~59second				Addr:0x200090
	unsigned int Accuracy_nSec_1;	//14bit	D29:D16		Max:1000,000,000ns 		Addr:0x200094
	unsigned int Accuracy_nSec_2;	//16bit	D15:D0								Addr:0x200098

	unsigned char Geodetic_Mode;	//1bit	D3			unuse:(0),use:(1)		Addr:0x2000A0
	unsigned char M_S_Mode;			//1bit	D2			Master:(0),Slave:(1)
	unsigned char TimeSync_Mode;	//2bit	D1:0		CV Sync:(00), PTP Sync:(01), External Clock Sysnc(10)

}_VME_Data;

#define M_CV_BUF_LEN      (15*2*1024)

typedef struct
{
	int full;
	int size;
	char b[M_CV_BUF_LEN];
	int i;
}_CV_Buf;

#define M_CV_BUF_SIZE      (2)
typedef struct {		/* CV Data */

	int Tick;					// CV Data 배열 선택 변수
	_CV_Buf Buf[M_CV_BUF_SIZE];	// CV Data 저장 배열
	int Rang_Count;				// CV Data인 Range 로그의 카운트
	int Satxyz_Count;			// CV Data인 Satxyz 로그의 카운트
	int CV_Trans_Period;		// CV Data 몇개 쌓아서 전송하는 가에대한 변수
	long time;					// 30분 카운트하여 CV Data 전송주기 5초->60초로 변경
	int Compare_Error;			// CV Data 일정시간 못할시 GPS 제어
	double CV_Value_Sum;
	int CV_Value_Sum_Count;

	char CV_Data_Disable;	// CV Data 전송 또는 전송하지 않게 하는 변수

}_CV_Data;

typedef struct {		/* VME Data */

	_VME_Data Data;
	_VME_BlockRam	BlockRam;

	char T1000ms;
	char T10ms;

	_CV_Data	CV_Data;
}_VME;

extern _VME VME;

extern int VME_init_count;
extern double  RAW_OFFSET;//RAW_DIFFERENCE,
extern double dbRlt_global;

extern void Init_VME();
extern void VME_Function();
extern void VME_Update_Data();
extern void VME_Update_BlockRam_Data();
extern void VME_Write_BlockRam();
extern void VME_Read_BlockRam();

extern void VME_Write(int addr,int data);
extern int VME_Read(int addr);
extern void VME_Interrupt();
extern void VME_BlockRam_Write(int addr,int data);
extern int VME_BlockRam_Read(int addr);

extern void PushCVData(char* p, unsigned int length);
extern void PopCVData();
extern int VME_CV_write(char * p, unsigned int length);

extern int CV_Data_Parse_string(char *cmdline, char *delim, char **argv);
extern int VME_CV_read();
extern void VME_Interrupt_handling();

extern void Initialization();

#endif /* VME_H_ */
